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NCP1652, NCP1652A
Peak Charger
V IN
HV
OUTA
V OUT
NCP1652
Figure 60. Peak charger
The startup circuit is rated at a maximum voltage of 500 V.
Power dissipation should be controlled to avoid exceeding
the maximum power dissipation of the controller. If
dissipation on the controller is excessive, a resistor can be
placed in series with the HV pin. This will reduce power
dissipation on the controller and transfer it to the series
resistor.
Drive Outputs
The NCP1652 has out off phase output drivers with an
Adjustable Dead Time
OUTA and OUTB have an adjustable dead time between
transitions to prevent simultaneous conduction of the main
and synchronous rectifier or active clamp MOSFETs. The
delay is also used to optimize the turn ? off transition of the
active clamp switch to achieve zero ? volt switching of the
main switch in an active clamp topology. Figure 61 shows
the timing relationship between OUTA and OUTB.
adjustable non ? overlap delay (t D ). The main output, OUTA,
drives the primary MOSFET. The secondary output, OUTB,
is designed to provide a logic signal used to control a
synchronous rectification switch in the secondary side, an
t delay (lead)
OUTA
t delay (trail)
active clamp switch in the primary or both. The outputs are
biased directly from V CC and their high state voltage is
approximately V CC .
OUTA has a source resistance of 13 W (typical) and a sink
resistance of 8.0 W (typical) OUTB has a source resistance
22 W (typical) and a sink resistance of 10 W (typical). OUTB
is a purposely sized smaller than OUTA because the gate
charge of an active switch or logic used with synchronous
rectification is usually less than that of the primary
MOSFET. If a higher drive capability is required, an external
discrete driver can be used.
The drivers are enabled once V CC reaches V CC(on) and
there are no faults present. They are disabled once V CC
discharges to V CC(off) . OUTB is always the last pulse
generated when the outputs are disabled due to a fault
(latch ? off, V CC(off) , overload, or brown ? out). The last pulse
terminates at the end of the clock cycle. This ensures the
active clamp capacitor is reset.
The high current drive capability of OUTA and OUTB
may generate voltage spikes during switch transitions due to
parasitic board inductance. Shortening the connection
length between the drivers and their loads and using wider
OUTB
Figure 61. Timing relationship between OUTA and
OUTB.
The dead time between OUTA and OUTB is adjusted by
connecting a resistor, R D , from the R D pin to ground. The
overlap delay is proportional to R D . The delay time can be
set between 80 ns and 1.8 m s using the formula:
t delay (in ns) + 8.0 R delay (in k W ) with
R delay varying between 10 k W and 230 k W
AC Error Amplifier and Buffer
The AC error amplifier (EA) shapes the input current into
a high quality sine wave by forcing the filtered input current
to follow the output of the reference generator. The output
of the reference generator is a full wave rectified ac signal
and it is applied to the non inverting input of the EA. The
filtered input current, I in , is the current sense signal at the
connections will reduce inductance ? induce spikes.
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